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Circuit Descriptions
EN 43Q549.2E LA 7.
2009-May-08
7.1.3 SSB Cell Layout
Figure 7-2 SSB layout cells (top view)
18310_201_090317.eps
090317
R
L
H
D
M
I
H
D
M
I
H
D
M
I
CA
1P00
HD
MI
1.3
USB
2.0
Y/C
Left
Right
CVBS
Head
Scart / YPbPr
SPO
R
serv
VGA
DDR2
DDR2
Tuner
DC/DC
1M99
1M71
1F02
1M59
1M20
1M01
1R12
1M36
TDA
98XX
Class-D
1R08
1R07
1HP0
1CJ0
Xilinx
Pr
Pb
L
Lo
Y
Ro
Scart / YPbPr
TDA
10048
TDA
10023
1
7
3
5
H
D
M
I
1M95
1
H
0
1
DDR2
DDR2
PNX8542/3
Video
In
Video
Out
DV in
TS in
HDMI B
HDMI A
PCI
CA
DDR
LVDS 2
LVDS 1
USB
Audio In
Audio
Out
E
J
T
A
G
STBY
GPIO
DDR
Ethernet
FLASH
HDMI
MUX
1E51
1E50
1G50
1G51
Wifi
L/R
1HE0
CY3
C40
H
D
M
I
RJ45
5100
40x40
1.27
DDR2
GPI
O
lvds-rx
ambi
pci/xio
PCI/
XIO
uart
I
²
C
vdi lvds-tx