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INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00
INTERRUPT MASK REGISTER (IMR)
The interrupt mask register, IMR (DDH, Set 1, and Bank0) is used to enable or disable interrupt processing for
individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their
required settings by the initialization routine.
Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on. When the IMR bit of
an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). When you set a level's
IMR bit to "1", interrupt processing for the level is enabled (not masked).
The IMR register is mapped to register location DDH in set 1and Bank0. Bit values can be read and written by
instructions using the register addressing mode.
NOTE:
Before IMR register is changed to any value, all interrupts must be disable.
Using DI instruction is recommended.
DDH, Set 1, Bank 0, R/W
Interrupt Mask Register (IMR)
.7 .6 .5 .4 .3 .2 .1 .0
MS
B
LSB
IRQ
1
IRQ
2
IRQ
3
IRQ
4
IRQ
6
IRQ
7
IRQ
0
0 = Disable (mask) interrupt
1 = Enable (un-mask) interrupt
Not
used
Interrupt Level Enable Bits (7-0):
Figure 5-6. Interrupt Mask Register (IMR)
5-10