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TIMER 2 S3F80P5_UM_ REV1.00
Timer2 Counter High-Byte Register (T2CNTH)
E4H , Set 1, Bank 1, Read-only
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
Reset Value: 00H
Timer 2 Counter Low-Byte Register (T2CNTL)
E5H , Set 1, Bank 1, Read-only
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
Reset Value: 00H
Timer 2 Data High-Byte Register (T2DATAH)
E6H , Set 1, Bank 1, R/W
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
Reset Value: FFH
Timer 2 Data Low-Byte Register (T2DATAL)
E7H , Set 1, Bank 1, R/W
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
Reset Value: FFH
Figure 13-5. Timer 2 Registers (T2CNTH, T2CNTL, T2DATAH, T2DATAL)
13-6