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S3F80P5_UM_ REV1.00 CONTROL REGISTERS
LVDCON — LVD Control Register E0H Set1 Bank1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
− − − − − − −
0
Read/Write
− − − − − − −
R/W
Addressing Mode
Register addressing mode only
.7− .1
Not used for S3F80P5.
.0 LVD Flag Indicator Bit
0
V
DD ≥
LVD_FLAG Level
1
V
DD
< LVD_FLAG Level
NOTE: When LVD detects LVD_FLAG level, LVDCON.0 flag bit is set automatically. When VDD is upper LVD_FLAG level,
LVDCON.0 flag bit is cleared automatically.
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