Filter
Top Products
Processor Configuration Memory population rules Memory population
information
populated in pairs, odd
amount of pairs allowed.
Dual CPU
NOTE:
Populate
round robin
starting with
CPU1
Advanced ECC
(Lockstep)
C1{1,2},C2{1,2},C1{3,4},C2{3,4}
….
Numbers inside the brackets
indicate the slots that must be
populated in pairs, odd
amount of pairs allowed.
Memory optimized (independent channel) mode
This mode supports Single Device Data Correction (SDDC) only for memory modules that use x4 device
width It does not impose any specific slot population requirements.
Memory installation guidelines:
Processor Configuration Memory population
rules
Memory
population
information
Single CPU
NOTE: Optimized mode permits
unbalanced configurations, eg,
1:1:1:0 DIMM per channel (DPC)
combinations.
Optimized
(independent
channel)
1, 2, 3, 4 Populate in this
order, odd amount
of DIMMs per CPU
allowed.
Dual CPU
NOTE: Populate round robin
starting with CPU1:
NOTE: Optimized mode permits
unbalanced configurations, eg,
2:1:1:1 DPC combinations.
Optimized
(independent
channel)
C1{1}, C2{1}, C1{2},
C2{2}, C1{3}, C2{3}…
Populate in this
order, odd amount
of DIMMs per CPU
allowed.
Memory mirroring
Memory Mirroring offers the strongest DIMM reliability mode compared to all other modes, providing
improved uncorrectable multi-bit failure protection. In a mirrored configuration, the total available
system memory is one half of the total installed physical memory. Half of the installed memory is used to
mirror the active DIMMs. In the event of an uncorrectable error, the system switches over to the mirrored
copy. This ensures SDDC and multi-bit protection.
Memory installation guidelines:
• Memory modules must be identical in size, speed, and technology.
• DIMMs installed in memory sockets with white release tabs must be identical and similar rule applies
for sockets with black release tabs. This ensures that identical DIMMs are installed in matched pairs -
for example, A1 with A2, A3 with A4.
NOTE:
Mirroring and Advanced ECC modes require minimum of two DIMMs per CPU and must be
populated in pairs of either two or four DIMMs per CPU.
42