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Rev. 1.0, 07/01, Page
xiii
of
xxiv
15.3.6 Slave Address Register (SAR).............................................................................232
15.3.7 I
2
C Bus Transmit Data Register (ICDRT)............................................................233
15.3.8 I
2
C Bus Receive Data Register (ICDRR).............................................................233
15.3.9 I
2
C Bus Shift Register (ICDRS)...........................................................................233
15.4 Operation...........................................................................................................................234
15.4.1 I
2
C Bus Format.....................................................................................................234
15.4.2 Master Transmit Operation..................................................................................235
15.4.3 Master Receive Operation....................................................................................237
15.4.4 Slave Transmit Operation ....................................................................................239
15.4.5 Slave Receive Operation......................................................................................241
15.4.6 Clocked Synchronous Serial Format....................................................................243
15.4.7 Noise Canceler.....................................................................................................245
15.4.8 Example of Use....................................................................................................246
15.5 Interrupt Request...............................................................................................................250
15.6 Bit Synchronous Circuit....................................................................................................251
Section 16 A/D Converter................................................................................. 253
16.1 Features.............................................................................................................................253
16.2 Input/Output Pins..............................................................................................................255
16.3 Register Description..........................................................................................................256
16.3.1 A/D Data Registers A to D (ADDRA to ADDRD)..............................................256
16.3.2 A/D Control/Status Register (ADCSR)................................................................257
16.3.3 A/D Control Register (ADCR).............................................................................258
16.4 Operation...........................................................................................................................259
16.4.1 Single Mode.........................................................................................................259
16.4.2 Scan Mode ...........................................................................................................259
16.4.3 Input Sampling and A/D Conversion Time .........................................................260
16.4.4 External Trigger Input Timing.............................................................................261
16.5 A/D Conversion Precision Definitions..............................................................................262
16.6 Usage Notes ......................................................................................................................263
16.6.1 Permissible Signal Source Impedance .................................................................263
16.6.2 Influences on Absolute Precision.........................................................................263
Section 17 Power-on Reset and Low-Voltage Detection Circuits (Optional) .. 265
17.1 Features.............................................................................................................................265
17.2 Register Descriptions ........................................................................................................266
17.2.1 Low-Voltage-Detection Control Register (LVDCR)...........................................266
17.2.2 Low-Voltage-Detection Status Register (LVDSR)..............................................268
17.3 Operation...........................................................................................................................268
17.3.1 Power-on Reset Circuit........................................................................................268
17.3.2 Low-Voltage Detection Circuit............................................................................269