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Rev. 1.0, 07/01, page 137 of 372
Section 11 Timer V
Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Compare-
match signals with two registers can also be used to reset the counter, request an interrupt, or
output a pulse signal with an arbitrary duty cycle. Counting can be initiated by a trigger input at
the TRGV pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary
delay from the trigger input. Figure 11-1 shows a block diagram of timer V.
11.1 Features
•
Choice of seven clock signals are available.
•
Choice of six internal clock sources (ø/128, ø/64, ø/32, ø/16, ø/8, ø/4) or an external clock (can
be used as an external event counter).
•
Counter can be cleared by compare match A or B, or by an external reset signal. If the count
stop function is selected, the counter can be halted when cleared.
•
Timer output is controlled by two independent compare match signals, enabling pulse output
with an arbitrary duty cycle, PWM output, and other applications.
•
Three interrupt sources: compare match A, compare match B, timer overflow
•
Counting can be initiated by trigger input at the TRGV pin. The rising edge, falling edge, or
both edges of the TRGV input can be selected.
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