Hitachi HD64F3694G TV Mount User Manual


 
Rev. 1.0, 07/01, page 73 of 372
Bit Bit Name Initial Value R/W Description
7 0 Reserved
This bit is always read as 0 and cannot be modified
6 MSTIIC 0 R/W IIC2 Module Standby
IIC2 enters the standby mode when this bit is set to 1
5 MSTS3 0 R/W SCI3 Module Standby
SCI3 enters the standby mode when this bit is set to 1
4 MSTAD 0 R/W A/D Converter Module Standby
A/D converter enters the standby mode when this bit is set
to 1
3 MSTWD 0 R/W Watchdog Timer Module Standby
Watchdog timer enters the standby mode when this bit is
set to 1.When the internal oscillator is selected for the
watchdog timer clock, the watchdog timer operates
regardless of the setting of this bit
2 MSTTW 0 R/W Timer W Module Standby
Timer W enters the standby mode when this bit is set to 1
1 MSTTV 0 R/W Timer V Module Standby
Timer V enters the standby mode when this bit is set to 1
0 MSTTA 0 R/W Timer A Module Standby
Timer A enters the standby mode when this bit is set to 1
6.2 Mode Transitions and States of the LSI
Figure 6-1 shows the possible transitions among these operating modes. A transition is made from
the program execution state to the program halt state by executing a SLEEP instruction. Interrupts
allow for returning from the program halt state to the program execution state. A direct transition
between the active mode and subactive mode, which are both program execution states, can be
made without halting the program. The operating frequency can also be changed in the same
modes by making a transition directly from active mode to active mode, and from subactive mode
to subactive mode. RES input enables transitions from a mode to the reset state. Table 6-2 shows
the transition conditions of each mode after the SLEEP instruction is executed and a mode to
return by an interrupt. Table 6-3 shows the internal states of the LSI in each mode.