Hitachi HD64F3694G TV Mount User Manual


 
Rev. 1.0, 07/01, page 189 of 372
Bit Bit Name Initial Value R/W Description
4 FER 0 R/W Framing Error
[Setting condition]
When a framing error occurs in reception
[Clearing condition]
When 0 is written to FER after reading FER =
1
3 PER 0 R/W Parity Error
[Setting condition]
When a parity error is detected during
reception
[Clearing condition]
When 0 is written to PER after reading PER =
1
2 TEND 0 R Transmit End
[Setting conditions]
When the TE bit in SCR3 is 0
When TDRE = 1 at transmission of the last bit
of a 1-frame serial transmit character
[Clearing conditions]
When 0 is written to TDRE after reading TDRE
= 1
When the transmit data is written to TDR
1 MPBR 0 R Multiprocessor Bit Receive
MPBR stores the multiprocessor bit in the receive
character data. When the RE bit in SCR3 is
cleared to 0, its state is retained.
0 MPBT 0 R/W Multiprocessor Bit Transfer
MPBT stores the multiprocessor bit to be added to
the transmit character data.