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Rev. 1.0, 07/01, page 45 of 372
Vector
Exception Sources Number Vector Address Priority
IIC2 Transmit data empty
Transmit end
Receive data full
NACK detection
Arbitration lost/Overrun error
Stop conditions detected
24 H'0030 to H'0031 High
A/D conversion end 25 H'0032 to H'0033 Low
Note : * A low-voltage detection interrupt is enabled only in the product with an on-chip power-on
reset and low-voltage detection circuit.
3.2 Register Descriptions
Interrupts are controlled by the following registers. For details on register addresses and register
states during each processing, refer to section 19, Internal I/O Register.
•
Interrupt Edge Select Register 1(IEGR1)
•
Interrupt Edge Select Register 2(IEGR2)
•
Interrupt Enable Register 1(IENR1)
•
Interrupt Flag Register 1(IRR1)
•
Wakeup Interrupt Flag Register(IWPR)
3.2.1
Interrupt Edge Select Register 1(IEGR1)
IEGR1 selects the direction of an edge that generates interrupt requests of pins
NMI
and
IRQ3
to
IRQ0
.
Bit Bit Name Initial Value R/W Description
7 NMIEG 0 R/W NMI Edge Select
0: Falling edge of NMI pin input is detected
1: Rising edge of NMI pin input is detected
6
5
4
−
−
−
1
1
1
−
−
−
Reserved
These bits are always read as 1, and cannot be modified.
3 IEG3 0 R/W IRQ3 Edge Select
0: Falling edge of IRQ3 pin input is detected
1: Rising edge of IRQ3 pin input is detected