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Rev. 1.0, 07/01, page 229 of 372
Bit Bit Name Initial Value R/W Description
5 RIE 0 R/W Receive Interrupt Enable
This bit enables or disables the receive data full interrupt
request (RXI) and the overrun error interrupt request (ERI)
with the clocked synchronous format, when a receive data
is transferred from ICDRS to ICDRR and the RDRF bit in
ICSR is set to 1. RXI can be canceled by clearing the
RDRF or RIE bit to 0.
0: Receive data full interrupt request (RXI) and overrun
error interrupt request (ERI) with the clocked
synchronous format are disabled.
1: Receive data full interrupt request (RXI) and overrun
error interrupt request (ERI) with the clocked
synchronous format are enabled.
4 NAKIE 0 R/W NACK Receive Interrupt Enable
This bit enables or disables the NACK receive interrupt
request (NAKI) and the overrun error (setting of the OVE bit
in ICSR) interrupt request (ERI) with the clocked
synchronous format, when the NACKF and AL bits in ICSR
are set to 1. NAKI can be canceled by clearing the NACKF,
OVE, or NAKIE bit to 0.
0: NACK receive interrupt request (NAKI) is disabled.
1: NACK receive interrupt request (NAKI) is enabled.
3 STIE 0 R/W Stop Condition Detection Interrupt Enable
0: Stop condition detection interrupt request (STPI) is
disabled.
1: Stop condition detection interrupt request (STPI) is
enabled.
2 ACKE 0 R/W Acknowledge Bit Judgement Select
0: The value of the receive acknowledge bit is ignored, and
continuous transfer is performed.
1: If the receive acknowledge bit is 1, continuous transfer is
halted.
1 ACKBR 0 R Receive Acknowledge
In transmit mode, this bit stores the acknowledge data that
are returned by the receive device. This bit cannot be
modified.
0: Receive acknowledge = 0
1: Receive acknowledge = 1