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Rev. 1.0, 07/01, Page
xv
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xxiv
Figures of Contents
Section 1 Overview
Figure 1-1 Internal Block Diagram of H8/3694 Series of the F-ZTAT
TM
and Mask-ROM Versions .............................................................................................2
Figure 1-2 Pin Arrangement of H8/3694 Series of the F-ZTAT
TM
and Mask-ROM Versions
(FP-64E, FP-64A).........................................................................................................3
Figure 1-3 Pin Arrangement of H8/3694 Series of the F-ZTAT
TM
and Mask-ROM Versions
(FP-48F)........................................................................................................................4
Section 2 CPU
Figure 2-1 Memory Map(1)............................................................................................................8
Figure 2-1 Memory Map(2)............................................................................................................9
Figure 2-2 CPU Registers.............................................................................................................10
Figure 2-3 Usage of General Registers.........................................................................................11
Figure 2-4 Relationship between Stack Pointer and Stack Area...................................................12
Figure 2-5 General Register Data Formats (1)..............................................................................14
Figure 2-5 General Register Data Formats (2)..............................................................................15
Figure 2-6 Memory Data Formats ................................................................................................16
Figure 2-7 Instruction Formats .....................................................................................................27
Figure 2-8 Branch Address Specification in Memory Indirect Mode...........................................30
Figure 2-9 On-Chip Memory Access Cycle..................................................................................33
Figure 2-10 On-Chip Peripheral Module Access Cycle (3-State Access) ....................................34
Figure 2-11 CPU Operation States................................................................................................35
Figure 2-12 State Transitions........................................................................................................36
Figure 2-13 Example of Timer Configuration with Two Registers Allocated to Same Address..37
Section 3 Exception Handling
Figure 3-1 Reset Sequence............................................................................................................51
Figure 3-2 Stack Status after Exception Handling........................................................................53
Figure 3-3 Interrupt Sequence ......................................................................................................54
Figure 3-4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure..............55
Section 4 Address Break
Figure 4-1 Block Diagram of an Address Break...........................................................................57
Figure 4-2 Address Break Interrupt Operation Example (1).........................................................60
Figure 4-2 Address Break Interrupt Operation Example (2).........................................................61
Figure 4-2 Address Break Interrupt Operation Example (3).........................................................62
Section 5 Clock Pulse Generators
Figure 5-1 Block Diagram of Clock Pulse Generators .................................................................63
Figure 5-2 Block Diagram of the System Clock Generator..........................................................64
Figure 5-3 Typical Connection to Crystal Oscillator....................................................................64
Figure 5-4 Equivalent Circuit of Crystal Oscillator......................................................................64