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Rev. 1.0, 07/01, page 146 of 372
ø
Compare match
A signal
Timer V output
pin
Figure 11-6 TMOV Output Timing
N H'00
ø
Compare match
A signal
TCNTV
Figure 11-7 Clear Timing by Compare Match
N – 1 N H'00
ø
Compare match
A signal
Timer V output
pin
TCNTV
Figure 11-8 Clear Timing by TMRIV Input
11.5 Timer V application examples
11.5.1 Pulse Output with Arbitrary Duty Cycle
Figure 11-9 shows an example of output of pulses with an arbitrary duty cycle.
1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with
TCORA.
2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA
and to 0 at compare match with TCORB.
3. Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source.