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Rev. 1.0, 07/01, page 63 of 372
Section 5 Clock Pulse Generators
Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a
system clock pulse generator and a subclock pulse generator. The system clock pulse generator
consists of a system clock oscillator, a duty correction circuit, and system clock dividers. The
subclock pulse generator consists of a subclock oscillator and subclock dividers.
Figure 5-1 shows a block diagram of the clock pulse generators.
System
clock
oscillator
Subclock
oscillator
Subclock
divider
Duty
correction
circuit
System
clock
divider
Prescaler S
(13 bits)
Prescaler W
(5 bits)
OSC
1
OSC
2
X
1
X
2
System clock pulse generator
ø
OSC
(f
OSC
)
ø
OSC
(f
OSC
)
ø
W
(f
W
)
ø
W
/2
ø
W
/4
ø
SUB
ø/2
to
ø/8192
ø
W
/8
ø
ø
OSC
/8
ø
OSC
ø
OSC
/16
ø
OSC
/32
ø
OSC
/64
ø
W
/8
to
ø
W
/128
Subclock pulse generator
Figure 5-1 Block Diagram of Clock Pulse Generators
The basic clock signals that drive the CPU and on-chip peripheral modules are ø and ø
SUB
. The
system clock is divided by prescaler S to become a clock signal from ø/8192 to ø/2, and the
subclock is divided by prescalerW to become a clock signal from øw/128 to øw/8. Both the system
clock and subclock signals are provided to the on-chip peripheral modules.
5.1 System Clock Generator
Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic
oscillator, or by providing external clock input. Figure 5-2 shows a block diagram of the system
clock generator.
CPG0200A0000_000020010700