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Rev. 1.0, 07/01, page 67 of 372
5.3 Prescalers
5.3.1 Prescaler S
Prescaler S is a 13-bit counter using the system clock (ø) as its input clock. The divided output is
used for the internal clock of on-chip peripheral modules. Prescaler S is initialized to H'0000 by a
reset, and starts counting on exit from the reset state. In standby mode, subactive mode, and
subsleep mode, the system clock pulse generator stops. Prescaler S also stops and is initialized to
H'0000. The CPU cannot read or write prescaler S. The output from prescaler S is shared by the
on-chip peripheral modules. The divider ratio can be set separately for each on-chip peripheral
function. In active mode and sleep mode, the clock input to prescaler S is determined by the
division factor designated by MA2 to MA0 in SYSCR2.
5.3.2 Prescaler W
Prescaler W is a 5-bit counter using a 32.768 kHz signal divided by 4 (ø
W
/4) as its input clock. The
divided output is used for clock time base operation of timer A. Prescaler W is initialized to H'00
by a reset, and starts counting on exit from the reset state. Even in standby mode, subactive mode,
or subsleep mode, prescaler W continues functioning so long as clock signals are supplied to pins
X
1
and X
2
. Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 of timer mode register
A (TMA).
5.4 Usage Notes
5.4.1 Note on Oscillators
Oscillator characteristics are closely related to board design and should be carefully evaluated by
the user, referring to the examples shown in this section. Oscillator circuit constants will differ
depending on the oscillator element, stray capacitance in its interconnecting circuit, and other
factors. Suitable constants should be determined in consultation with the oscillator element
manufacturer. Design the circuit so that the oscillator element never receives voltages exceeding
its maximum rating.