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Rev. 1.0, 07/01, page 48 of 372
3.2.4 Interrupt Flag Register 1(IRR1)
IRR1 is a status flag register for direct transition interrupts, timer A overflow interrupts, and IRQ3
to IRQ0 interrupt requests.
Bit Bit Name Initial Value R/W Description
7 IRRDT 0 R/W Direct Transfer Interrupt Request Flag
[Setting condition]
When a direct transfer is made by executing a SLEEP
instruction while DTON in SYSCR2 is set to 1.
[Clearing condition]
When IRRDT is cleared by writing 0
6 IRRTA 0 R/W Timer A Interrupt Request Flag
[Setting condition]
When the timer A counter value overflows
[Clearing condition]
When IRRTA is cleared by writing 0
5
4
−
−
1
1
−
−
Reserved
These bits are always read as 1, and cannot be modified.
3 IRRI3 0 R/W IRQ3 Interrupt Request Flag
[Setting condition]
When IRQ3 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IRRI3 is cleared by writing 0
2 IRRI2 0 R/W IRQ2 Interrupt Request Flag
[Setting condition]
When IRQ2 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IRRI2 is cleared by writing 0
1 IRRI1 0 R/W IRQ1 Interrupt Request Flag
[Setting condition]
When IRQ1 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IRRI1 is cleared by writing 0
0 IRRl0 0 R/W IRQ0 Interrupt Request Flag
[Setting condition]
When IRQ0 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IRRI0 is cleared by writing 0