Filter
Top Products
C
C-6 Micro PLC Programmer’s Guide – April 1994
GFK-0804B
Hardware Implementation of CRC-16
CRC-16 can be implemented using a multi–section shift register (which is based on the
generating polynomial):
13 12 11 10 9 8 7 6 5 4 3 2 115 14 0
+ ++
CRC Register
X
16
X
15
X
2
LSB
+ = Exclusive OR
Data
Input
40473
The message data bits are fed to the Shift Register one at a time. The CRC register
contains a preset value. As each data bit is presented to the Shift Register, the bits are
shifted to the right. The LSB is XORed with the data bit and the result is: XORed with
the old contents of bit 1 (the result placed in bit 0), XORed with the old contents of bit 14
(and the result placed in bit 13), and finally, it is shifted into bit 15. This process is
repeated until all data bits in a message have been processed.
Software Calculation of CRC–16
The pseudo code for software calculation of the CRC–16 is given below.
Preset byte count for data to be sent.
Initialize the 16–bit remainder (CRC) register to all ones.
XOR the first 8–bit data byte with the high order byte of the
16–bit CRC register. The result is the current CRC.
INIT SHIFT: Initialize the shift counter to 0.
SHIFT: Shift the current CRC register 1 bit to the right.
Increment shift count.
Is the bit shifted out to the right (flag) a 1 or a 0?
If it is a 1, XOR the generating polynomial with the current CRC.
If it is a 0, continue.
Is shift counter equal to 8?
If NO, return to SHIFT.
If YES, increment byte count.
Is byte count greater than the data length?
If NO, XOR the next 8–bit data byte with the current CRC
and go to INIT SHIFT.
If YES, add current CRC to end of data message
for transmission and exit.
When the message is transmitted, the receiver will perform the same CRC operation on
all the data bits and the transmitted CRC. If the information is received correctly the
resulting remainder (receiver CRC) will be 0.