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MELSEC-
A
5 PRELIMINARY INFORMATION
(1) When using the RIWT command
This is used only when writing to the R2-designated buffer memory.
When using the RIWT command, the master station buffer memory will be used
as the transmission buffer for the control data and write data.
The complete status will be stored in the reception buffer.
(Example) Writing in the reception complete data size and reception timeout
time
R2
R2 111
H
0
H
to 1FF
H
M
R2 112
H
Programmable controller CPU
Master module
(Transmission buffer)
Refer to control data (a)
Address
1000
H
to 11FF
H
M
of Q/QnA Series
of A Series bank 1
Address
One word
each
Write
data
Reception complete data size designation
Reception timeout time designation
Reception complete data size designation
area
Reception timeout time designation area
(Reception buffer)
Complete status
Station No., request code
Address
Q/QnA Series A Series
Bank 1
+
1200
H
M
200
H
M
Bank 1
+
1201
H
M
201
H
M
(a) Control data
Note that the control data differs between the QCPU (Q mode)/QnACPU
and ACPU/QCPU-A (A mode) as shown below.
One word
each
One word
each
When using ACPU/QCPU-A (A mode) When using QCPU (Q mode)/QnACPU
Control data Control data
Complete status Complete status
Station No.No. of write points (words)
No. of write points (words)
Access code, attribute Access code, attribute
Buffer memory address
Buffer memory address