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Rev. 1.0, 07/01, page 79 of 372
Legend
tosc: OSC clock cycle time
tw: Watch clock cycle time
tcyc: System clock (ø) cycle time
tsubcyc: Subclock (ø
SUB
) cycle time
6.4.2 Direct Transition from the Subactive Mode to the Active Mode
The time from the start of SLEEP instruction execution to the end of interrupt exception handling
(the direct transition time) is calculated by equation (2).
Direct transition time = {(number of SLEEP instruction execution states) + (number of internal
processing states)} × (tsubcyc before transition) + {(waiting time set in bits STS2 to STS0) +
(number of interrupt exception handling states)} × (tcyc after transition) (2)
Example
Direct transition time = (2 + 1) × 8tw + (8192 + 14) × tosc = 24tw + 8206tosc
(when the CPU operating clock of ø
w
/8 → ø
osc
and a waiting time of 8192 states are selected)
Legend
tosc: OSC clock cycle time
tw: Watch clock cycle time
tcyc: System clock (ø) cycle time
tsubcyc: Subclock (ø
SUB
) cycle time
6.5 Module Standby Function
The module-standby function can be set to any peripheral module. In the module standby mode,
the clock supply to modules stops to enter the power-down mode. The module standby mode
enables each on-chip peripheral module to enter the standby state by setting a bit that corresponds
to each module to 1 and cancels the mode by clearing the bit to 0.