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Rev. 1.0, 07/01, page 316 of 372
V
IH
V
IL
t
IL
to
to
TMCI
FTIOA to FTIOD
TMCIV, TMRIV
TRGV
t
IH
Figure 20-3 Input Timing
SCL
V
IH
V
IL
t
STAH
t
BUF
P* S*
t
Sf
t
Of
t
Sr
t
SCL
t
SDAH
t
SCLH
t
SCLL
SDA
Sr*
t
STAS
t
SP
t
STOS
t
SDAS
P*
Note: * S, P, and Sr represent the following:
S: Start condition
P: Stop condition
Sr: Retransmission start condition
Figure 20-4 I
2
C Bus Interface Input/Output Timing
t
Scyc
t
SCKW
SCK3
Figure 20-5 SCK3 Input Clock Timing