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Rev. 1.0, 07/01, page 238 of 372
TDRE
TEND
ICDRS
ICDRR
[1] Clear TDRE after clearing
TEND and TRS
[2] Read ICDRR (dummy read)
[3] Read ICDRR
1
A
2134567899
A
TRS
RDRF
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
Bit 7
Master transmit mode Master receive mode
Bit 7Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
User
processing
Data 1
Data 1
Figure 15-7 Master Receive Mode Operation Timing (1)
RDRF
RCVD
ICDRS
ICDRR
Data n-1
Data n
Data n
Data n-1
[5] Read ICDRR after setting RCVD
[6] Issue stop
condition
[7] Read ICDRR,
and clear RCVD
[8] Set slave
receive mode
19 23456789
AA/
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
User
processing
Figure 15-8 Master Receive Mode Operation Timing (2)