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Rev. 1.0, 07/01, page 182 of 372
Clock
TXD
RXD
SCK3
BRR
SMR
SCR3
SSR
TDR
RDR
TSR
RSR
Transmit/receive
control circuit
Internal data bus
Legend
RSR:
RDR:
TSR:
TDR:
SMR:
SCR3:
SSR:
BRR:
BRC:
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register 3
Serial status register
Bit rate register
Bit rate counter
Interrupt request
(TEI, TXI, RXI, ERI)
Internal clock (ø/64, ø/16, ø/4, ø)
External
clock
BRC
Baud rate generator
Figure 14-1 Block Diagram of SCI3