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Rev. 1.0, 07/01, page 72 of 372
6.1.2 System Control Register 2(SYSCR2)
The SYSCR2 register controls the power-down modes, as well as SYSCR1.
Bit Bit Name Initial Value R/W Description
7
6
5
SMSEL
LSON
DTON
0
0
0
R/W
R/W
R/W
Sleep Mode Selection
Low Speed on Flag
Direct Transfer on Flag
These bits select the mode to enter after the execution of
a SLEEP instruction, as well as bit SSBY of SYSCR1.
For details, see table 6-2.
4
3
2
MA2
MA1
MA0
0
0
0
R/W
R/W
R/W
Active Mode Clock Select 2 to 0
These bits select the operating clock frequency in the
active and sleep modes. The operating clock frequency
changes to the set frequency after the SLEEP instruction
is executed.
0XX: φ
OSC
100: φ
OSC
/8
101: φ
OSC
/16
110: φ
OSC
/32
111: φ
OSC
/64
1
0
SA1
SA0
0
0
R/W
R/W
Subactive Mode Clock Select 1 and 0
These bits select the operating clock frequency in the
subactive and subsleep modes. The operating clock
frequency changes to the set frequency after the SLEEP
instruction is executed.
00: φ
W
/8
01: φ
W
/4
1X: φ
W
/2
Legend X: Don't care.
6.1.3 Module Standby Control Register 1(MSTCR1)
MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units.