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Rev. 1.0, 07/01, page 268 of 372
17.2.2 Low-Voltage-Detection Status Register (LVDSR)
LVDSR is an 8-bit readable/writable register which indicates whether or not the power-supply
voltage has become lower or higher than the respective specified values.
Bit Bit Name
Initial
Value R/W Description
7 to 2 − 1 − Reserved
These bits are always read as 1, and cannot be modified.
1 LVDDF 0 R/W LVD Enable
[Setting condition]
The power-supply voltage falling below the lower value specified
by LVDSEL in LVDCR
[Clearing condition]
Writing 0 to this bit after reading it as 1
0 LVDUF 0 R/W LVD Enable
[Setting condition]
The power supply voltage rising above the upper value specified
by LVDSEL in LVDCR
[Clearing condition]
Writing 0 to this bit after reading it as 1
17.3 Operation
17.3.1 Power-on Reset Circuit
Figure 17-2 shows the timing of the operation of the power-on reset circuit. As the power-supply
voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via
the on-chip pull-up resistance (approximately 150 kΩ). Since the state of the RES pin is
transmitted within the chip, the prescaler S and the entire chip are in their reset states. When the
level on the RES pin reaches the specified value, the prescaler S is released from its reset state and
it starts counting. The OVF signal is generated to release the internal reset signal after the
prescaler S has counted 131,072 clock (φ) cycles.
Design the power-supply circuit so that the voltage rises to its full level and settles within the
specified time. The size of the capacitor should be determined with regard to the time required for
the power supply to rise and settle after power has been supplied. The noise cancellation circuit of
approximately 100 ns is incorporated to prevent the incorrect operation of the chip by noise on the
RES pin.