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Hitachi H*/3694F-ZTAT TV Mount User Manual

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Rev. 1.0, 07/01, page 222 of 372

SCL

ICCR1

Transfer clock

generation

circuit

Address

comparator

Interrupt

generator

Interrupt request

Bus state

decision circuit

Arbitration

decision circuit

Noise canceler

Noise canceler

Output

control

Output

control

Transmission/

reception

control circuit

ICCR2

ICMR

ICSR

ICEIR

ICDRR

ICDRS

ICDRT

I

2

C bus control register 1

I

2

C bus control register 2

I

2

C bus mode register

I

2

C bus status register

I

2

C bus interrupt enable register

I

2

C bus transmit data register

I

2

C bus receive data register

I

2

C bus shift register

Slave address register

Legend

ICCR1 :

ICCR2 :

ICMR :

ICSR :

ICIER :

ICDRT :

ICDRR :

ICDRS :

SAR :

SAR

SDA

Internal data bus

Figure 15-1 Block Diagram of I

2

C Bus Interface 2

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