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Rev. 1.0, 07/01, page 230 of 372
Bit Bit Name Initial Value R/W Description
0 ACKBT 0 R/W Transmit Acknowledge
In receive mode, this bit specifies the bit to be sent at the
acknowledge timing.
0: 0 is sent at the acknowledge timing.
1: 1 is sent at the acknowledge timing.
15.3.5 I
2
C Bus Status Register (ICSR)
ICSR is an 8-bit readable/writable register that performs confirmation of interrupt request flags
and status.
Bit Bit Name Initial Value R/W Description
7 TDRE 0 R/W Transmit Data Register Empty
[Setting condition]
•
When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
[Clearing conditions]
•
When 0 is written in TDRE after reading TDRE = 1
•
When data is written to ICDRT with an instruction
6 TEND 0 R/W Transmit End
[Setting conditions]
•
When the ninth clock of SCL rises with the I
2
C bus
format while the TDRE flag is 1
•
When the final bit of transmit frame is sent with the clock
synchronous serial format
[Clearing conditions]
•
When 0 is written in TEND after reading TEND = 1
•
When data is written to ICDRT with an instruction