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Rev. 1.0, 07/01, page
xvi
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xxiv
Figure 5-5 Typical Connection to Ceramic Oscillator..................................................................65
Figure 5-6 Example of External Clock Input................................................................................65
Figure 5-7 Block Diagram of the Subclock Generator .................................................................65
Figure 5-8 Typical Connection to 32.768-kHz Crystal Oscillator................................................66
Figure 5-9 Equivalent Circuit of 32.768-kHz Crystal Oscillator..................................................66
Figure 5-10 Pin Connection when not Using Subclock................................................................66
Figure 5-11 Example of Incorrect Board Design..........................................................................68
Section 6 Power-down Modes
Figure 6-1 Mode Transition Diagram...........................................................................................74
Section 7 ROM
Figure 7-1 Flash Memory Block Configuration ...........................................................................82
Figure 7-2 Programming/Erasing Flowchart Example in User Program Mode............................89
Figure 7-3 Program/Program-Verify Flowchart ...........................................................................91
Figure 7-4 Erase/Erase-Verify Flowchart.....................................................................................94
Figure 7-5 Socket Adapter Pin Correspondence Diagram............................................................97
Figure 7-6 Timing Waveforms for Memory Read after Memory Write.......................................98
Figure 7-7 Timing Waveforms in Transition from Memory Read Mode to Another Mode.........99
Figure 7-8 CE and OE Enable State Read Timing Waveforms..................................................100
Figure 7-9 CE and OE Clock System Read Timing Waveforms................................................100
Figure 7-10 Auto-Program Mode Timing Waveforms...............................................................102
Figure 7-11 Auto-Erase Mode Timing Waveforms....................................................................103
Figure 7-12 Status Read Mode Timing Waveforms ...................................................................104
Figure 7-13 Oscillation Stabilization Time, Boot Program Transfer Time,
and Power-Down Sequence ....................................................................................106
Section 9 I/O Ports
Figure 9-1 Port 1 Pin Configuration ...........................................................................................111
Figure 9-2 Port 2 Pin Configuration ...........................................................................................116
Figure 9-3 Port 5 Pin Configuration ...........................................................................................118
Figure 9-4 Port 7 Pin Configuration ...........................................................................................123
Figure 9-5 Port 8 Pin Configuration ...........................................................................................126
Figure 9-6 Port B Pin Configuration...........................................................................................129
Section 10 Timer A
Figure 10-1 Block Diagram of Timer A .....................................................................................132
Section 11 Timer V
Figure 11-1 Block Diagram of Timer V .....................................................................................138
Figure 11-2 Increment Timing with Internal Clock....................................................................144
Figure 11-3 Increment Timing with External Clock...................................................................145
Figure 11-4 OVF Set Timing......................................................................................................145
Figure 11-5 CMFA and CMFB Set Timing................................................................................145
Figure 11-6 TMOV Output Timing............................................................................................146
Figure 11-7 Clear Timing by Compare Match............................................................................146