Rev. 1.0, 07/01, page 2 of 372
1.2 Internal Block Diagram
P10/TMOW
P11
P12
P14/
P15/
P16/
P17/ /TRGV
P50/
P51/
P52/
P53/
P54/
P55/ /
P56/SDA
P57/SCL
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
V
CC
V
SS
V
CL
TEST
AV
CC
P20/SCK3
P21/RXD
P22/TXD
P80/FTCI
P81/FTIOA
P82/FTIOB
P83/FTIOC
P84/FTIOD
P85
P86
P87
P74/TMRIV
P75/TMCIV
P76/TMOV
OSC1
OSC2
X1
X2
CPU
H8/300H
ROM
RAM
SCI3
Port 1
Timer W
IIC2
Timer A
Watchdog
timer
Timer V
A/D
converter
Subclock
generator
System
clock
generator
Port 2
Port B Port 5 Port 7 Port 8
Data bus (upper)
Address bus
Data bus (lower)
Figure 1-1 Internal Block Diagram of H8/3694 Series of the F-ZTAT
TM
and Mask-ROM
Versions