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Rev. 1.0, 07/01, page 44 of 372
Table 3-1 Exception Sources and Vector Address
Vector
Exception Sources Number Vector Address Priority
Reset 0 H'0000 to H'0001 High
Reserved for system use 1 to 6 H'0002 to H'000D
NMI 7 H'000E to H'000F
Trap instruction (#0) 8 H'0010 to H'0011
(#1) 9 H'0012 to H'0013
(#2) 10 H'0014 to H'0015
(#3) 11 H'0016 to H'0017
Break conditions satisfied 12 H'0018 to H'0019
Direct transition by executing the SLEEP instruction 13 H'001A to H'001B
IRQ0
Low-voltage detection interrupt*
14 H'001C to H'001D
IRQ1 15 H'001E to H'001F
IRQ2 16 H'0020 to H'0021
IRQ3 17 H'0022 to H'0023
WKP 18 H'0024 to H'0025
Timer A Overflow 19 H'0026 to H'0027
Reserved for system use 20 H'0028 to H'0029
Timer W Input capture A/compare match A
Input capture B/compare match B
Input capture C/compare match C
Input capture D/compare match D
Timer W overflow
21 H'002A to H'002B
Timer V Timer V compare match A
Timer V compare match B
Timer V overflow
22 H'002C to H'002D
SCI3 SCI3 receive data full
SCI3 transmit data empty
SCI3 transmit end
SCI3 receive error
23 H'002E to H'002F
Low