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Rev. 1.0, 07/01, page 251 of 372
15.6 Bit Synchronous Circuit
In master mode,this module has a possibility that high level period may be short in the two states
described below.
•
When SCL is driven to low by the slave device
•
When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pull-
up resistance)
Therefore, it monitors SCL and communicates by bit with synchronization.
Figure 15-21 shows the timing of the bit synchronous circuit and table 15-4 shows the time when
SCL output changes from low to Hi-Z then SCL is monitored.
SCL
VIH
SCL monitor
timing reference
clock
Internal SCL
Figure 15-21 The Timing of the Bit Synchronous Circuit
Table 15-4 Time for Monitoring SCL
CKS3 CKS2 Time for Monitoring SCL
0 7.5 tcyc0
1 19.5 tcyc
0 17.5 tcyc1
1 41.5 tcyc