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Rev. 1.0, 07/01, page 224 of 372
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I
2
C bus receive data register (ICDRR)
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I
2
C bus shift register (ICDRS)
15.3.1 I
2
C Bus Control Register 1 (ICCR1)
ICCR1 is an 8-bit readable/writable register that enables or disables the I
2
C bus interface, controls
transmission or reception, and selects master or slave mode, transmission or reception, and
transfer clock frequency in master mode.
Bit Bit Name Initial Value R/W Description
7ICE 0 R/WI
2
C Bus Interface Enable
0: This module is halted. (SCL and SDA pins are set to port
function.)
1: This bit is enabled for transfer operations. (SCL and SDA
pins are bus drive state.)
6 RCVD 0 R/W Reception Disable
This bit enables or disables the next operation when TRS is
0 and ICDRR is read.
0: Enables next reception
1: Disables next reception
5
4
MST
TRS
0
0
R/W
R/W
Master/Slave Select
Transmit/Receive Select
In master mode with the I
2
C bus format, when arbitration is
lost, MST and TRS are both reset by hardware, causing a
transition to slave receive mode. Modification of the TRS bit
should be made between transfer frames.
Operating modes are described below according to MST
and TRS combination. When clocked synchronous serial
format is selected and MST is 1, clock is output.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
3
2
1
0
CKS3
CKS2
CKS1
CKS0
0
0
0
0
R/W
R/W
R/W
R/W
Transfer Clock Select 3 to 0
These bits are valid only in master mode and should be set
according to the necessary transfer rate. For details on
transfer rate, see table 15-2, Transfer Rate.