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Fig. 11-1 Block diagram
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D/A
D/A
D/A
R
G
B
Ys
RAM (8
∗
8
∗
12bit)
∗
3
Q715
Q717
Q719
Q705
Q704
Q703
GH
GV
BH
BV
RV
RH
Counter
PLL
HD
VD
Q707
Q719
32MHz
Q767
M-CON
DATA
CLK
RESET
R716, C711
E
2
PROM
MEMORY
Q701 T7K64
Load
Save
Q713
Main bus line
Test pattern