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2 Operation
• When "td" (= 30msec) passes after the voltage reaches 4.25V by
turning on the power, the output is drive to HIGH.
"td" is set by the external capacitor (C106).
Block diagram
(12) Operation panel
1 General
• The operation circuit is composed of the key matrix circuit and the
display matrix circuit.
Key detection: With the signal detected by Q1 ∼ Q7 and KI0 ∼ KI3
signal matrix at LOW (GND) and Q2 ∼ Q7 at HIGH (open), the
level of KI 0 ∼ KI3 is checked to judge whether key matrix 1, 2, and
3 are HIGH or LOW, judging on/off.
For Q2 ∼ Q7, switching is made every 2msec to judge each of
them.
R1
R2
1.25V
+
-
-
Power
5µA
reference
GND Delay capacity
Output
t
ta ta
H
L
Output not constant
ta = 30m sec
t
4.25V
0.65V
Power voltageOutput state
KI0
KI1
KI2
321
Q4
M66313
+5V2 +5V1
CPU
TD62504
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