Filter
Top Products
213
Chapter 5: Reference
Error Messages
NOTE: For labels that do span pod pairs, the complexity can be reduced to the same
as that of the non-split label case if all bits in the label on all but one pod pair
can be set to Xs in the event list expression for the measurement.
For example, if label ADDR has its 16 most significant bits on pod A3 and
16 least significant bits on pod A2 (spanning pod pairs A4/A3 and A2/A1),
the complexity of the compiled expression will be reduced if all 16 most
significant bits or all 16 least significant bits are set to Xs in the pattern
event.
• Inequality compares (<,<=,>,>=) of split labels increases the expression
complexity compared to equality (=,!=) compares of split labels. There is
no difference in complexity for non-split labels.
• Ranges are implemented as two inequality compares which doubles the
required complexity for non-split labels but compounds the complexity to
an even greater extent for ranges on split patterns.
• Equivalent event list expressions compile to a MUCH greater hardware
complexity in 400/800/1250/1500 Mb/s state modes than in 200 Mb/s state
mode. This is due to the way the hardware implements these faster state
modes. The hardware parallelizes the data to allow the internal sequencer
to still run at <= 200 Mb/s. However, this requires the trigger compiler to
allocate additional sequence levels, branches, and pattern resources and
combine them in complex expressions to de-parallelize the trigger
expression. Using split labels in these faster modes further multiplies the
complexity of these compiler generated expressions.
• The trigger compiler first expands all expression lists to sum-of-products
form (for example, A(B+C) is expanded to AB+AC). The trigger compiler
then does rudimentary boolean reduction on the expanded expression.
However, the compiler does make some trade-offs between complete
reduction and compile speed. Manually expanding and reducing a complex
expression may help the trigger compiler to better fit the expression into
the hardware resources.
Specific Guidelines - 200 Mb/s State and all Timing Modes
• Cannot OR more than 16 non-split pattern events if the pattern events are
all on the same pod pair.
• Cannot OR more than 4 non-split pattern events if each pattern event is on
a different pod pair. You can, however, OR 4 patterns together on each of 4
different pod pairs to make a total of 16 patterns ORed across 4 pod pairs.