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Chapter 2: Probing and Selecting the Sampling Mode
Choosing the Sampling Mode
NOTE: If all pods are used, memory depth is reduced by half in order to store the
required time tags.
NOTE: With the Sample Period at 2.5 ns, data is acquired at two times the trigger
sequencer rate. This means that data must be present for at least two samples
before the trigger sequencer can reliably detect it. The trigger sequencer
could miss data present for less than two sample periods.
The trigger sequencer treats the data as a group of two samples for each
sequencer clock. This means that the trigger point indication could be off by
one sample.
Although the trigger sequencer cannot detect all data, the analyzer will
correctly capture all data present for at least one sample period.
See Also “To specify default storing” on page 76
“How Samples are Stored in Transitional Timing” on page 157
“Default Storing Subtab” on page 190
To specify the sample period
When the logic analyzer is in timing (asynchronous sampling) mode,
the Sample Period setting specifies how often the logic analyzer
samples the signals from the device under test.
1. In the Sampling tab, with Timing Mode selected, enter the desired time
between logic analyzer samples.
To capture signal level changes reliably, the sample period should be less
than half (many engineers prefer one-fourth) of the period of the fastest
signal you want to measure.
The sample rate is the inverse of the sample period.
NOTE: In the conventional timing configuration, the sample rate is fixed at 1.25 ns.