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Chapter 2: Probing and Selecting the Sampling Mode
Formatting Labels for Logic Analyzer Probes
Capturing Data on 17
Channels in State
Mode
On a single-card 16760A logic analyzer in the state (synchronous)
sampling mode, you can assign pod 2 to the logic analyzer and unassign
pod 1. (One pod must be unassigned in order to store time tags.) Even
though pod 1 is unassigned, its J clock input is still used as the
sampling clock input. This allows the 16 channels and the K clock input
on pod 2 to be used as data sampling channels. This lets you capture
data on high-speed buses that have 17 data bits, and a clock.
When you assign pods this way, the logic analyzer loses its ability to
detect, to prevent triggering or sequencing on, and to remove an initial
spurious sample in the acquisition (which can occur if the logic
analyzer measurement is started before the state clock input signal
starts toggling). However, because most high-speed devices have
continuously running periodic clocks, the appearance of an initial
spurious sample is unlikely.
When the K clock input is used as a data channel like this, it cannot be
used as a qualifier signal for eye scan measurements (unless the data
signal also happens to be the necessary clock qualification input for eye
scan).
See Also “To set up qualified eye scan measurements” on page 122
“Selecting the State Mode (Synchronous Sampling)” on page 46
To set pod threshold voltages
The threshold voltage is the voltage level that a signal must cross
before the logic analyzer recognizes a change in logic levels.
1. In the Format tab, select the threshold button located just below the pod
name.
2. In the Pod threshold dialog, either:
• Select the Standard option; then, select one of the predefined
threshold voltages from the drop-down list.
• Select the External Ref option. This option appears when the E5378A
single-ended probe is used. It should be selected when the probe's
threshold voltage reference inputs are used and are connected to the