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4.6.2 Bus Access of Big Endian
The data format in the FR20 series is normally big endian. Thus, external bus access is
big endian for areas in which little endian (LER) is not set.
■ Data Format
The relationship between the internal register and external data bus is indicated per data format.
●
Half-word access (LDUH, STH instruction execution)
Figure 4.6-2 Relationship between the internal register and external data bus of half-word access
●
Byte access (LDUH, STH instruction execution)
Figure 4.6-3 Relationship between internal register and external data bus of byte access
■ Data Bus Width
The relationship between the internal register and external data bus is indicated per data bus width.
b) Output address Lower"10"
D31
D15
D23
D7
D0
AA
BB
Internal register
D31
D15
D23
D7
D0
AA
BB
External bus
a) Output address Lower"00"
D31
D15
D23
D7
D0
AA
BB
Internal register
D31
D15
D23
D7
D0
AA
BB
External bus
D31
D15
D23
D7
D0
AA
Internal register
D31
D15
D23
D7
D0
AA
External bus
Internal register
External bus
Internal register
External bus
Internal register
External bus
a) Output address Lower"00"
D31
D15
D23
D7
D0
AA
D31
D15
D23
D7
D0
AA
b) Output address Lower"01"
D31
D15
D23
D7
D0
AA
D31
D15
D23
D7
D0
AA
c) Output address Lower"10"
D31
D15
D23
D7
D0
AA
D31
D15
D23
D7
D0
AA
d) Output address Lower"11"