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CHAPTER 3 CPU
3.12.3 Timebase Timer Clear Register (CTBR)
This register initializes the timebase timer contents to 0.
■ Timebase Timer Clear Register (CTBR)
Figure 3.12-5 Timebase timer clear register (CTBR)
[bit7 to 0]
Writing A5
H
, 5A
H
continuously to this register clears the timebase timer to 0 immediately after 5A
H
.
The reading value of this register is irregular. There is no restriction on the time interval between A5
H
and 5A
H
writing.
Note:
Clearing the timebase timer using this register temporarily fluctuates oscillation stability wait interval,
watchdog cycle, and peripheral cycles that use the timebase.
D7 D6 D5 D4 D3 D2 D1 D0 XXXX XXXX
B
Initial value
76543210
Address: 000483
H
WWWWWWWW
Access
bit