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■ Capture Control Register (CAPC)
Figure 7.2-3 Capture control register (CAPC)
[bit7, 6, 5, 4]:
It is an unused bit.
[bit3]:FUL
It is FIFO full flag.
[bit2]:EMP
It is FIFO empty flag.
[bit1]:CLR
It is FIFO clear control bit.
The read value of this bit is always "0".
[bit0]:INC
It is FIFO output control bit.
The read value of this bit is always "0".
7 6 5 4 3 2 1 0
---- 0100
B
Initial value
bit
EMP CLR INCFUL
WWRR
Access
Address: 000067
H
0 Status which affords to input the data to FIFO
1 Status of FIFO full
0 Status which data is remained in FIFO
1 Status of FIFO empty
0 None
1 Clear FIFO.
0 None
1 Output next data on FIFO.