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CHAPTER 18 10-bit General-purpose Prescaler
[bit0]:ST
It is operation enable bit.
■
Data Register (GPRD)
Figure 18.2-2 Data Register (GPRDH)
Figure 18.2-3 Data Register (GPRDL)
The division operation set to this register is performed. When "N" is set, the clock output frequency "fn" is
below.
fn =1/{Φ × (N+1)}
Use half-word access commands to write to this register. (Byte access command cannot be written.)
0
Operation stop
1 Enabling operations
7 6 5 4 3 2 1 0
---- --XX
B
Initial value
bit
D9
D8
Address: 000032
H
Access
WW
7 6 5 4 3 2 1 0
XXXX XXXX
B
Initial value
bit
WWWWWWWW
D1 D0D3 D2D5 D4D7 D6
Address: 000033
H
Access