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Appendix E Instruction List
Note:
• "2/1" of CYCLE number is following;
2: branching
1: not branching
• The assembler calculates and sets values as follows in the rel11 and rel8 fields for hardware specifications.
(label12-PC-2)/2→rel11, (label9-PC-2)/2→rel8, label12, label9 are with sign.
• When executing RETI instruction, S flag is required to be "0".
■
Delay Divergence Instruction
Table E-14 Delay divergence Instruction
Mnemonic Type OP CYCLE NZVC Operation Remark
JMP:D @Ri E 9F-0 1 ---- Ri
→
PC
CALL:D label12
CALL:D @Ri
F
E
D8
9F-1
1
1
----
----
PC+4
→
RP,
PC+2+(label12-PC-2)→
PC
PC+4
→
RP,Ri
→
PC
RET:D E 9F-2 1 ---- RP
→
PC Return
BRA:D label9
BNO:D label9
BEQ:D label9
BNE:D label9
BC:D label9
BNC:D label9
BN:D label9
BP:D label9
BV:D label9
BNV:D label9
BLT:D label9
BGE:D label9
BLE:D label9
BGT:D label9
BLS:D label9
BHI:D label9
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
----
----
----
----
----
----
----
----
----
----
----
----
----
----
----
----
PC+2+(label9-PC-2)
→
PC
not diverge
if(Z==1)then
PC+2+(label9-PC-2) →
PC
↑
s/Z==0
↑
s/C==1
↑
s/C==0
↑
s/N==1
↑
s/N==0
↑
s/V==1
↑
s/V==0
↑
s/VxorN==1
↑
s/VxorN==0
↑
s/(VxorN)orZ==1
↑
s/(VxorN)orZ==0
↑
s/CorZ==1
↑
s/CorZ==0
Note:
• The assembler calculates and sets values as follows in the rel11 and rel8 fields for hardware specifications.
(label12-PC-2)/2->rel11, (label9-PC-2)/2→rel8, label12, label9 are with sign.
• In terms of delayed branches, branching must be implemented after executing the next command (delay slot).
• Commands that can be placed at the delay slot are all 1 cycle, a, b, c, and d cycle commands.
Two or more-cycle instruction cannot be put.