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st r2,@r7 // asr3,amr3 register write
st r3,@r8 // asr4,amr4 register write
st r4,@r9 // asr5,amr5 register write
init_ler ldi:8 #0x02,r0 // CH2 little endian
ldi:20 #0x7fe,r1 // ler register address setting
stb r0,@r1 // ler register write
init_modr ldi:8 #0x80,r0 // External ROM external bus
ldi:20 #0x7ff,r1 // modr register address setting
stb r0,@r1 // modr register write
// external bus access
adr_set ldi:32 #0x00136da0, r0 // ch1 address
ldi:32 #0x00151300, r1 // ch2 address
ldi:32 #0x00196434, r2 // ch4 address (within the page)
ldi:32 #0x0019657c, r3 // ch4 address (within the page)
ldi:32 #0x00196600, r4 // ch4 address (outside of the page)
ldi:32 #0x001a6818, r5 // ch5 address (within the page)
ldi:32 #0x001a6b8c, r6 // ch5 address (within the page)
ldi:32 #0x001a6c00, r7 // ch5 address (outside of the page)
bus_acc ld @r0,r8 // ch1 data word load
lduh @r1,r9 // ch2 data half word load
ld @r2,r10 // ch4 data word load
ldub @r3,r11 // ch4 data byte load
st r8,@r4 // ch4 data word store
sth r9,@r5 // ch5 data half word store
st r10,@r6 // ch5 data word store
stb r11,@r7 // ch5 data byte store