Filter
Top Products
181
9.2 Register of Real Timing Generator (RTG)
The register configuration/functions of the real timing generator (RTG) are described.
■ RTGx Control Register (RTGxC)
Figure 9.2-1 RTGx Control Register (RTGxC)
[bit7]:IF
It is output timing data match interrupt request flag.
[bit6]:FCLR
It is interrupt request flag clear bit.
The read value of this bit is always "1".
[bit5]:IE
It is interrupt enable bit.
[bit4]:OUTE
It is output enable bit.
[bit3]:TSEL
It is timing accuracy selection bit of RTG section (RTG0 to 2).
7 6 5 4 3 2 1 0
X100 0001
B
Initial value
bit
Access
Address: 000034
H
(RTG0C)
000038
H
(RTG1C)
00003C
H
(RTG2C)
RWR/W WRRR/W R/W
IF FCLR IE OUTE TSEL
CLR FUL EMP
0 Not match
1 Match
0 Clear IF.
1 None
0 Interrupt interdiction
1 Interrupt permission
0 RTG output interdiction (Low output fixed)
1 RTG output enable
0 400 ns accuracy (in fch=@20 MHz)
1 800 ns accuracy (in fch=@20 MHz)