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CHAPTER 10 Timer
[bit1]:IFLG
It is match detection flag.
[bit0]:TIE
It is interrupt enable bit.
■ Timer Data Register H, L (TxDRH, TxDRL)
Figure 10.3-3 Timer data register H, L (TxDRH, TxDRL)
The counter is cleared by the register that sets the value to be compared with the counter value when
matched with the counter value.
■ Timer Count Register H, L (TxCDH, TxCDL)
Figure 10.3-4 Timer count register H, L (TxCDH, TxCDL)
0 No match detection
1 Match detection
0 Interrupt interdiction
1 Interrupt permission
7 6 5 4 3 2 1 0
XXXX XXXX
B
Initial value
bit
R/W R/WR/W R/WR/W R/WR/W R/W
Access
7 6 5 4 3 2 1 0
XXXX XXXX
B
Initial value
bit
R/W R/WR/W R/WR/W R/WR/W R/W
Access
7 6 5 4 3 2 1 0
XXXX XXXX
B
Initial value
bit
RRRRRRRR
Access
7 6 5 4 3 2 1 0
XXXX XXXX
B
Initial value
bit
RRRRRRRR
Access