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CHAPTER 3 CPU
[Operation]
1. SSP-4 → SSP
2. PS → (SSP)
3. SSP-4 → SSP
4. Address of the following instruction→(SSP)
5. Interrupt level of accepted request→ ILM
6. "0" → S Flag
7. (TBR + Vector offset of accepted interrupt request)→ PC
Prior to execute the front command of the handler after the interrupt sequence ends, a new EIT is detected.
At this stage, if an acceptable EIT is generated, the CPU transits to the EIT processing sequence.
■ Operation of INT Instruction
The INT #u8 instruction operates as follow.
Branch to the interrupt handler for the vector indicated by u8.
[Operation]
1. SSP-4 → SSP
2. PS → (SSP)
3. SSP-4 → SSP
4. PC+2 → (SSP)
5. "0" → I Flag
6. "0" → S Flag
7. (TBR+3FCH - 4 × u8)→ PC
■ Operation of INT Instruction
The INT instruction operates as follow.
Branch to the interrupt handler for the vector indicated by vector number #9.
[Operation]
1. SSP-4 → SSP
2. PS → (SSP)
3. SSP-4 → SSP
4. PC+2 → (SSP)
5. "00100" → ILM
6. "0" → S Flag
7. (TBR+3D8H)→ PC
Do not use the INTE instruction during the INTE instruction and step trace trap processing routine.
Moreover, EIT is not generated while executing the step by INTE.