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CHAPTER 3 CPU
■ Coprocessor Absent Trap
When a coprocessor command using an unmounted coprocessor is executed, a coprocessor absence trap is
generated.
[Operation]
1. SSP-4 → SSP
2. PS → (SSP)
3. SSP-4 → SSP
4. Address of the following instruction→(SSP)
5. "0" → S Flag
6. (TBR+3E0H)→ PC
■ Coprocessor Error Trap
If an error occurs while using a coprocessor, when the coprocessor command that operates the coprocessor
is executed next, a coprocessor error trap is generated.
[Operation]
1. SSP-4 → SSP
2. PS → (SSP)
3. SSP-4 → SSP
4. Address of the following instruction→(SSP)
5. "0" → S Flag
6. (TBR+3DCH)→ PC
Note:
This product does not contain the coprocessor.
■ Operation of RETI Instruction
The RETI instruction is an instruction which returns from EIT processing routine.
[Operation]
1. (R15) → PC
2. R15+4 → R15
3. (R15) → PS
4. R15+4 → R15
Care must be taken that the stack pointer to be referred to returning of the PS and PC is selected in
accordance with the S flag contents. When the command that operates R15 (stack pointer) within the
interrupt handler is executed, set the S flag to "1" and use the USP as R15. The S flag must be returned to
"0" before the RETI command.
■ Delay Slot
In the delay slot of the branch instruction, there is a restriction concerning EIT.
Refer to "3.8.1 Branch Command with Delay Slot" for details.