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105
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Byte access (LDUB, STB instruction execution)
Figure 4.6-10 Relationship between internal register and external data bus of byte access
■ Data Bus Width
●
32-bit bus width
Figure 4.6-11 Relationship between internal register and external data bus of 32-bit bus width
●
16-bit bus width
Figure 4.6-12 Relationship between internal register and external data bus of 16-bit bus width
D31
D15
D23
D7
D0
AA
Internal register
D31
D15
D23
D7
D0
AA
External bus Internal register External bus Internal register External bus Internal register External bus
a) Output address Lower "00" b) Output address Lower "01" c) Output address Lower "10" d) Output address Lower "11"
D31
D15
D23
D7
D0
AA
D31
D15
D23
D7
D0
AA
D31
D15
D23
D7
D0
AA
D31
D15
D23
D7
D0
AA
D31
D15
D23
D7
D0
AA
D31
D15
D23
D7
D0
AA
D07
D15
D23
D31
External bus
Internal register
AA
BB
CC
DD
read/write
DD
CC
BB
AA
D07
D15
D23
D31
D07
D15
D23
D31
D23
D31
"00" "10"
External busInternal register
Output address lower
AA
BB
CC
DD
BB
AA
DD
CC
read/write