Filter
Top Products
28
CHAPTER 3 CPU
are required to execute commands for the load/store command to which memory wait is attached, branch
commands that do not have delay slots, and multi-cycle commands. Also, when the supplied instruction is
slow, the execution speed of the instruction decrease.
Refer to "3.8 Overview of Instructions" for details.
●
32-bit ↔ 16-bit bus converter
Interfaces between the D-BUS that quickly accesses at 32-bit width and the R-BUS that accesses at 16-bit
width, and realizes data access from the CPU to built-in peripheral circuit.
When 32-bit width access is performed from the CPU, this bus converter accesses the R-BUS by
converting it to 16-bit width access twice. Some of built-in peripheral circuits have access width-related
restrictions.
●
Harvard ↔ Princeton bus converter
Coordinates between the CPU command access and data access, and realizes smooth interface with the
external bus.
In CPU, the instruction bus and the data bus are the independent Harvard architecture structures. On the
other hand, the bus controller that controls the external bus has a Princeton architectural structure with a
single bus. This bus converter ranks the priority order for command access and data access of the CPU, and
controls access to the bus controller. This operation always optimizes the external bus access ranking.
It also has a two-word write buffer to eliminate CPU bus waiting time and a one-word pre-fetch buffer to
fetch commands.