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Interrupt level mask register (ILM)
Figure 3.3-11 shows the configuration of the interrupt level mask register (ILM).
Figure 3.3-11 Interrupt level register (ILM)
The interrupt level mask register (ILM) retains the interrupt level mask value, and values retained by this
ILM are used as the level mask.
Interrupt requests are received only when the supported interrupt level is higher than the level indicated by
this ILM out of the interrupt requests to be input to the CPU.
As for the level value, 0(00000
B
) is the strongest, and 31(11111
B
) is weakest.
There is a limitation in the value which can be set from the program.
If the original value is between 16 to 31, the new value must be between 16 to 31. When the command
setting 0 to 15 is executed, the value (specified value + 16) is transferred.
If the original value is between 0 to 15, an arbitrary value between 0 to 31 can be set.
This register is initialized to 15 (01111
B
) by a reset.
20 19 18 17 16 Initial value
ILM4 ILM3 ILM2 ILM1 ILM0 01111
H
bit