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10.4 Operation of 16-bit Timer (Timer 0 to 4)
In terms of the 16-bit timer, the internal clock can be selected from four types by setting
the clock source selection bit (TC1, TC0) of the timer control register (TxCRL). The timer
data register (TxDRH, TxDRL) will be the one used for setting the interval time, and
reading the timer count data register (TxCDH, TxCDL) enables the timer count value to
be known.
■ Operation of 16-bit Timer (Timer 0 to 4)
When the timer starts up, counting begins after the counter is cleared to "0000
H
" by writing "1" to the timer
start bit (TSTR) of the timer control register "L" after setting the interval time to the timer data register. The
compare latch of the timer data register is loaded immediately after writing if the timer is suspended.
Matching the counter value with the set value of the compare latch sets the match detection flag (IFLG) to
"1". In this case, the counter is cleared to "0000
H
" if the load request flag is set, the data register value is
loaded to the compare latch, and counting continues. In terms of the interval time "T", when "n" is selected
as the data register set value, and "φ" is selected as the selection clock, the interval time "T" becomes
below.
T= Φ × (n+1) The toggle output frequency fTO is as follow.
fTO=1/{Φ × (n+1) × 2}
Figure 10.4-1 Operation of 16-bit timer
Counter clear
data setting value
Compare latch
Count value
0000
H
TSTR
LFLG
IFLG
TxO
LREQ=1(W)
FCLR=0(W)
LREQ=1(W)
FCLR=0(W) FCLR=0(W)
EQ EQ EQ